10+ years combined hardware design experience
Involved in the design of 3 VLSI chips
ASIC Design for state-of-the-art technology in 0.35u, 0.25u, and 0.13u
RTL Modeling in VHDL and Verilog
Design Tools: Cadence, Synopsis
Processors: ARM, VLIW
Emulation: Xilinx, Altera
Scripting: perl, tcl, csh